Introduction to Design Verification

Skills you will demonstrate

Describe the best-practice DV strategies applied currently to semiconductor digital designs
Understand the main methodologies, tools and languages used in those best-practice DV strategies
Apply those DV methodologies, tools and languages to basic digital designs
Analyse a “real” semiconductor digital design and suggest an appropriate DV strategy
Understand current best-practice DV sufficiently to enable participants to discuss DV topics confidently with colleagues

After completing the course participants will have sufficient understanding of DV tools and
methodologies to contribute effectively to real projects

Format

The course runs over 1 month with the following main activities:

1. 8 online one-hour lectures covering the major Design Verification topics
2. 4 online one-hour lectures covering Debug
3. Access to tools in the cloud for running online exercises
4. Access to online Cadence courses using the latest languages, tools and techniques

Note that participants will get additional support outside the lectures and exercises as needed.

Preparatory and follow-on reading will be suggested but neither are obligatory. There is no (summative or formative) assessment.

Prerequisites

None. The course is suitable for a wide range of people working in semiconductor design & development, especially recent graduates. Although not a perquisite, some experience of programming (preferably with an Object-Oriented language) would be useful.

Assessment and certification

The course be attendance only with no assessment. Participants who attend the course will receive the following:

• For completing parts 1 and 2: students will receive a Continuing Professional Development and a TechWorks Academy certificate
• For completing part 3: A Cadence certificate of accomplishment and also a digital badge of accomplishment, which the students can include in their LinkedIn profile

Project plan

Week 1

Session 1: Introduction
Session 2: Simulation-based Verification

Week 2

Session 3: Hardware design and verification languages
Session 4: Q&A and Exercises
Session 5: The Verification Cycle

Week 3

Session 6: Stimuli generation and checking
Session 7: Q&A and Introduction to debug
Session 8: Coverage

Week 4

Session 9: Assertion Based Verification
Session 10: Q&A and Making debug efficient
Session 11: Verification in practise

Week 5

Session 12: Making debug effective
Session 13: Making debug effective
Session 14: Test bench qualification